A prior art System on Chip (SoC) employing semiconductor features sizes of 28 nm implements automatic dynamic voltage scaling (AVS) with an external voltage regulator. Typically the AVS is limited to a certain voltage range determined by the differential in voltages allowed between a static random access memory (SRAM) bit cell minimum voltage and surrounding logic. For this prior art device the AVS voltage is typically scaled between 1 V and 0.72 V.
The flip flop designs in the corresponding circuit library may retain their state at even lower voltages. In a known semiconductor manufacturing process, the retention voltage is around 0.5 V. Potential leakage current savings could be accomplished by lowering the voltage even below the typical automatic DVS scaled voltage. In an example digital signal processor of the Texas Instruments TMS320C6600 family, lowering the voltage below the AVS voltage could reduce the leakage current by 40 to 60% when the DSP is idle.